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IDT74FCT163543A

IDT74FCT163543A DataSheet IDT 3.3V CMOS 16-BIT LATCHED TRANSCEIVER

3.3V CMOS 16-BIT LATCHED TRANSCEIVER

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---Full Text Search Engine--- IDT74FCT163543A
---Full Text Search Engine--- 3.3V CMOS 16-BIT LATCHED TRANSCEIVER

IDT74FCT163543C IDT74FCT163543A 74FCT163543_DS_62380

IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
IDT74FCT163543A/C
* 0.5 MICRON CMOS Technology * Typical tSK(o) (Output Skew) < 250ps * ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) * VCC = 3.3V  0.3V, Normal Range, or VCC = 2.7V to 3.6V, Extended Range * CMOS power levels (0.4 W typ. static)  * Rail-to-rail output swing for increased noise margin * Low Ground Bounce (0.3V typ.) * Inputs (except I/O) can be driven by 3.3V or 5V components * Available in SSOP and TSSOP packages
FEATURES:
DESCRIPTION:
The FCT163543 16-bit latched transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit D-type latched transceivers with separate input and output control to permit independent control of data flow in either direction. For example, the A-to-B Enable (xCEAB) must be low in order to enter data from the A port or to output data from the B port. xLEAB controls the latch function. When xLEAB is low, the latches are transparent. A subsequent low-to-high transition of xLEAB signal puts the A latches in the storage mode. xOEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using xCEBA, xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT163543 have series current limiting resistors. These offer low ground bounce, minimal undershoot, and controlled output fall times- reducing the need for external series terminating resistors.
FUNCTIONAL BLOCK DIAGRAM
1OEBA 56 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB
54 55 1 3 2
2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB
29 31 30 28 26 27
C
1A1 5 2A1
C
52
D C D
1B1
D C D
42
2B1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
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(c) 2002 Integrated Device Technology, Inc.
MAY 2002
DSC-3250/5
IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1OEAB 1LEAB 1CEAB
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current Max -0.5 to +4.6 -0.5 to 7 -0.5 to VCC+0.5 -65 to +150 -60 to +60 Unit V V V C mA
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
1OEBA 1LEBA 1CEBA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
VTERM(2) VTERM(3) VTERM(4) TSTG IOUT
GND
1A1 1A2
GND
1B1 1B2
VCC
1A3 1A4 1A5
VCC
1B3 1B4 1B5
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Vcc terminals. 3. Input terminals. 4. Outputs and I/O terminals.
GND
1A6 1A7 1A8 2A1 2A2 2A3
GND
1B6 1B7 1B8 2B1 2B2 2B3
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 3.5 3.5 Max. 6 8 Unit pF pF
GND
2A4 2A5 2A6
GND
2B4 2B5 2B6
NOTE: 1. This parameter is measured at characterization but not tested.
VCC
2A7 2A8
VCC
2B7 2B8
FUNCTION TABLE(1, 3)
Inputs xLEAB X H L H L H
GND
2CEAB 2LEAB 2OEAB
FOR A-TO-B (SYMMETRIC WITH B-TO-A)
Latch Status xAx to xBx Storing Storing Transparent Storing Transparent Storing Output Buffers xBx Z X Current A Inputs Previous(2) A Inputs Z Z
GND
2CEBA 2LEBA 2OEBA
SSOP/ TSSOP TOP VIEW
PIN DESCRIPTION
Pin Names xOEAB xOEBA xCEAB xCEBA xLEAB xLEBA xAx xBx Description A-to-B Output Enable Input (Active LOW) B-to-A Output Enable Input (Active LOW) A-to-B Enable Input (Active LOW) B-to-A Enable Input (Active LOW) A-to-B Latch Enable Input (Active LOW) B-to-A Latch Enable Input (Active LOW) A-to-B Data Inputs or B-to-A 3-State Outputs B-to-A Data Inputs or A-to-B 3-State Outputs
xCEAB H X L L L L
xOEAB X X L L H H
NOTES: 1. A-to-B data flow shown; B-to-A flow control is the same, except using xCEBA, xLEBA and xOEBA. 2. Before xLEAB LOW-to-HIGH Transition 3. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High-Impedance
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IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Industrial: TA = -40C to +85C, VCC = 2.7V to 3.6V
Symbol VIH VIL IIH IIL IOZH IOZL VIK IODH IODL VOH Parameter Input HIGH Level (Input pins) Input HIGH Level (I/O pins) Input LOW Level (Input and I/O pins) Guaranteed Logic LOW Level Input HIGH Current (Input pins) Input HIGH Current (I/O pins) Input LOW Current (Input pins) Input LOW Current (I/O pins) High Impedance Output Current (3-State Output pins) Clamp Diode Voltage Output HIGH Current Output LOW Current Output HIGH Voltage VCC = Min., IIN = -18mA VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V VCC = Min. VIN = VIH or VIL VCC = 3V VIN = VIH or VIL VOL Output LOW Voltage VCC = Min. VIN = VIH or VIL VCC = 3V VIN = VIH or VIL IOS VH ICCL ICCH ICCZ Short Circuit Current Input Hysteresis Quiescent Power Supply Current VCC = Max. VIN = GND or VCC
(4) (3) (3)
Test Conditions(1) Guaranteed Logic HIGH Level
Min. 2 2 -0.5
Typ.(2) -- -- -- -- -- -- -- -- -- -0.7 -60 90 -- 3 3 -- 0.2 0.3 0.3 -135 150 0.1
Max. 5.5 VCC+0.5 0.8 1 1 1 1 1 1 -1.2 -110 200 -- -- -- 0.2 0.4 0.55 0.5 -240 -- 10
Unit V V A
VCC = Max.
VI = 5.5V VI = VCC VI = GND VI = GND
-- -- -- -- -- -- -- -36 50 VCC-0.2 2.4 2.4
(5)
VCC = Max.
VO = VCC VO = GND
A
V mA mA V
IOH = -0.1mA IOH = -3mA IOH = -8mA IOL = 0.1mA IOL = 16mA IOL = 24mA IOL = 24mA
-- -- -- -- -60
V
VCC = Max., VO = GND(3) --
mA mV A
-- --
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. VOH = VCC-0.6V at rated current.
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IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol ICC ICCD Parameter Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN = VCC -0.6V(3) VCC = Max., Outputs Open xCEAB and xOEAB = GND xCEBA = VCC One Input Toggling 50% Duty Cycle VCC = Max., Outputs Open fi = 10MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC One Bit Toggling VCC = Max., Outputs Open fi = 2.5MHz 50% Duty Cycle xLEAB, xCEAB and xOEAB= GND xCEBA = VCC Sixteen Bits Toggling VIN = VCC VIN = GND Min. -- -- Typ.(2) 2 60 Max. 30 100 Unit A A/ MHz
IC
Total Power Supply Current(6)
VIN = VCC VIN = GND VIN = VCC -0.6V VIN = GND VIN = VCC VIN = GND VIN = VCC -0.6V VIN = GND
--
0.6
1
mA
--
0.6
1
--
2.4
4(5)
--
2.4
4.3(5)
NOTES: 1. For conditions shown as max. or min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 3.3V, +25C ambient. 3. Per TTL driven input; all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + DICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ICC = Power Supply Current for a TTL High Input DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi
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IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(1)
Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tSU tH tW tSK(o) Parameter Propagation Delay Transparent Mode xAx to xBx or xBx to xAx Propagation Delay xLEBA to xAx, xLEAB to xBx Output Enable Time xOEBA or xOEAB xAx or xBx xCEBA or xCEAB xAx or xBx Output Disable Time xOEBA or xOEAB xAx or xBx xCEBA or xCEAB xAx or xBx Set-up Time HIGH or LOW xAx or xBx to xLEAB or xLEBA Hold Time HIGH or LOW xAx or xBx to xLEAB or xLEBA xLEBA or xLEAB Pulse Width LOW Output Skew(4) Condition(2) CL = 50pF RL = 500 FCT163543A Min.(3) Max. 1.5 6.5 FCT163543C Min.(3) Max. 1.5 5.3 Unit ns
1.5 1.5
8 9
1.5 1.5
7 8
ns ns
1.5
7.5
1.5
6.5
ns
2 2 5 --
-- -- -- 0.5
2 2 5 --
-- -- -- 0.5
ns ns ns ns
NOTES: 1. Propagation Delays and Enable/Disable times are with VCC = 3.3V 0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays and Enable/Disable times should be degraded by 20%. 2. See test circuit and waveforms. 3. Minimum limits are guaranteed but not tested on Propagation Delays. 4. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
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IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T. 50pF CL 500 VOUT 6v Open GND
SWITCH POSITION
Test Open Drain Disable Low Enable Low Disable High Enable High All Other Tests Switch 6V GND Open
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
1.5V
1.5V
tSU
tH
Pulse Width
Set-up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH 6V tPZH SWITCH GND 3V 1.5V tPHZ 0.3V 1.5V 0V 0V VOH tPLZ DISABLE 3V 1.5V 0V 3V 0.3V VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate  1.0MHz; tF  2.5ns; tR  2.5ns. 3. if VCC is below 3V, input voltage swings should be adjusted not to exceed VCC.
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IDT74FCT163543A/C 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT FCT XXX XX Temp. Range Family XXXX Device Type X Package
PV PA
Shrink Small Outline Package Thin Shrink Small Outline Package
543A 543C 163 74
16-Bit Latched Transceiver
Double-Density 3.3Volt - 40C to +85C
DATA SHEET DOCUMENT HISTORY
4/22/2002 5/21/2002 Removed blank speed grade Removed TVSOP package
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