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MSM98S000

MSM98S000 DataSheet ETC[ETC] 0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays

0.8m Mixed 3-V/5-V Gates Customer Structured Arrays

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MSM98S000 MSM38S0000 MSM38S0000 MSM98S MSM38S0000 MSM98S MSM98S000

DATA SHEET
O K I A S I C P R O D U C T S
0.8m Mixed 3-V/5-V MSM38S0000 Sea of Gates and MSM98S000 Customer Structured Arrays
February 1995
TRADEMARKS
AIX, DOS, PC, and Windows are trademarks, and IBM is a registered trademark of IBM Corporation Apollo, Domain, and DomainOS are trademarks of Apollo Computer, a subsidiary of Hewlett-Packard AutoLogic, IDEA, QuickFault, QuickGrade, QuickPath, QuickSim, and Mentor Graphics are trademarks of Mentor Graphics Corporation Composer, Concept, HDL, Leapfrog, PLI, Veritime, and VHDL are trademarks, and Cadence, DRACULA, TestScan, Verifault, and Verilog are registered trademarks of Cadence Design Systems, Inc. Design Compiler, HDL/VHDL Compiler, Test Compiler, and VSS are trademarks of Synopsys, Inc. HP and HP-UX are trademarks of Hewlett-Packard Company Alchemy and IKOS are trademarks of IKOS Systems, Inc. Powerview, Viewlogic, ViewRetargeter, ViewSim, ViewSynthesis, and Workview are trademarks of Viewlogic Systems, Inc. Solaris, Sun, Sun-3, Sun-4, and SunOS are trademarks of Sun Microsystems, Inc. UNIX is a registered trademark of UNIX System Laboratories, Inc. All other products or services mentioned in this document are identified by the trademarks, service marks, or product names as designated by the companies who market those products. Inquiries concerning such trademarks should be made directly to those companies. OKI Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by OKI Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by OKI Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of OKI.
OKI SEMICONDUCTOR
MSM38S0000/MSM98S000
0.8m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays DESCRIPTION
OKI's 0.8m ASIC products, specially designed for mixed 3-V/5-V applications, are now available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM38S Series and the CSA-based MSM98S Series use a three-layer-metal process on 0.8m drawn (0.6m L-effective) CMOS technology. The semiconductor process is adapted from OKI's production-proven 16-Mbit DRAM manufacturing process. The MSM38S SOG Series is available in seven sizes with up to 420 I/O pads and over 135,000 usable gates. SOG array sizes are designed to fit the most popular quad flat pack (QFP) packages, such as 100-, 136-, 160-, and 208-pin QFPs. MSM38S SOG-based designs are therefore ideal for pad-limited circuits that require rapid prototyping turnaround times.
Ideal for low-power portable applications, the MSM38S/98S are constructed with separate power busses for internal core logic and configurable I/O functions. Altogether, the architecture provides maximum flexibility, meeting the needs of all 3-V, 5-V, and mixed 3-V/5-V signal requirements. The MSM98S CSA Series is an all-mask-level superset of the SOG series, available in 29 sizes. The CSA offerings combine the SOG architecture's logic flexibility with the higher integration yielded by optimized diffusion for faster and more compact memory blocks. The MSM98S is ideal for core-limited applications or circuits with large and/or multiple memory functions. Customer modification to the structure of any of the 29 predefined masterslices, rather than creation of a new masterslice every time, improves the prototyping turnaround time over cell-based manufacturing techniques. Both product families are supported by OKI's proprietary MEMGEN tool which quickly and easily generates SOG memories (for the MSM38S) as well as optimized memories for the MSM98S Series. The families also feature floorplanning to control pre-layout timing, clock-skew management software that guarantees worst-case clock skew of 1 ns or less, and scan-path design techniques that support ATVG for fault coverage approaching 100%.
FEATURES
* 0.8m drawn three-layer metal CMOS * Mixed 3-V/5-V operation for low power and high speed * SOG and CSA architecture availability * Clock tree cells with  1.0-ns clock skew, worst-case (fan-out = 2000 at 70 MHz) * Usable density from 6.5k to 135k gates * I/Os may be VSS, 3 V, 5 V, VDD, CMOS, TTL, and 3state, with 2-mA to 48-mA drive
* I/O level shifter cells, allowing any buffer (input, output, or bidirectional) to interface with 3 V or 5 V * Slew-rate-controlled outputs for low radiated noise * User-configurable single and multi-port memories * Specialized 3-V and 5-V macrocells, including phaselocked loop, and PCI cells * Floorplanning for front-end simulation and back-end layout controls * JTAG boundary scan and scan-path ATVG OKI SEMICONDUCTOR 1
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
MSM38S/98S FAMILY LISTING
CSA Part # MSM... 98S020x020 98S023x023 -- 98S026x026 98S029x029 98S032x032 -- 98S035x035 98S038x038 -- 98S041x041 98S044x044 98S047x047 98S050x050 98S053x053 -- 98S056x056 98S059x059 98S062x062 98S065x065 98S068x068 -- 98S071x071 98S074x074 98S077x077 98S080x080 98S083x083 98S086x086 98S089x089 98S092x092 98S095x095 98S098x098 98S101x101 98S104x104 -- SOG Part # MSM... -- -- 38S0110 -- -- -- 38S0210 -- -- 38S0300 -- -- -- -- -- 38S0570 -- -- -- -- -- 38S0980 -- -- -- -- -- 38S1500 -- -- -- -- -- -- 38S2250 I/O Pads 80 92 100 104 116 128 136 140 152 160 164 176 188 200 212 216 224 236 248 260 272 280 284 296 308 320 332 344 356 368 380 392 404 416 420 Rows[1] 44 51 56 59 66 74 79 81 89 94 96 104 111 119 126 129 134 141 149 156 164 169 171 179 186 194 201 209 216 224 231 239 246 254 256 Columns 148 176 194 200 228 252 270 276 304 322 328 356 380 408 432 442 456 484 508 536 560 580 588 612 636 664 688 716 740 768 792 816 844 868 880 Raw Gates 6,512 8,976 10,752 11,800 15,048 18,648 21,172 22,356 27,056 30,080 31,488 37,024 42,180 48,552 54,432 56,760 61,104 68,244 75,692 83,616 91,840 97,344 100,548 109,548 118,296 128,816 138,288 149,644 159,840 172,032 182,952 195,024 207,624 220,472 224,256 Usable Gates 4,689 6,463 7,741 8,496 10,835 13,427 15,244 16,096 19,480 21,658 22,671 25,917 29,526 33,986 38,102 39,732 42,162 47,088 51,471 56,859 62,451 66,194 67,367 72,302 75,709 82,442 88,504 95,772 99,101 103,219 109,771 117,014 124,574 132,283 134,554
[2]
[1] Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. For example, a 7,600-gate mega macrocell with a size and aspect ratio of 36 rows by 245 columns can be used on the MSM98S032x032 or any larger array base, but not on the MSM98S029x029. [2] Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, RAM/ROM blocks, etc.
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OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
ARRAY ARCHITECTURE
The primary components of a 0.8m MSM38S/98S circuit include: * * * * * * *
Each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO for 3 V and VSSO).
I/O cells include level shifter Separate power bus for internal core logic Column of Gates
I/O base cells Configurable I/O pads for VDD, VSS, or I/O (I/O in both 3V and 5V) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility
Configurable I/O pads for VDD (3.3 V), VDD (5 V), VSS, I/O (3.3 V), or I/O (5 V)
Core Area VDD = 3.3 or 5 V
Four-transistor basic core cell
VDD, VSS pads in each corner for wafer probing only VSSO
VDDO (5 V) VDDO (3.3 V)
Separate power bus over I/O cell for output buffers (VDDO (3.3 V), VDDO (5 V), VSSO)
Figure 1. MSM38S/98S Array Architecture MSM98S000 CSA Layout Methodology The procedure to design, place, and route a CSA follows.
1. Select suitable base array frame from the available predefined sizes. To select an array size:
OKI SEMICONDUCTOR
- Identify the macrocell functions required and the minimum array size to hold the macrocell functions.
3
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
2. Make a floor plan for the design's megacells.
- Add together all the area occupied by the required random logic and macrocells and select the optimum array.
Figure 2 shows an array base after placement of the optimized memory macrocells.
- OKI Design Center engineers verify the master slice and review simulation. - OKI Design Center engineers floorplan the array using OKI's proprietary floorplanner and customer performance specifications. - Using OKI CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications.
Early mask high-density ROM Mega macrocell High-density RAM
Multi-port RAM
Figure 2. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors.
Figure 3 marks the area in which placement and routing is performed with light shading.
- OKI Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells.
Figure 3. Random Logic Place and Route
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OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Output current per I/O base cell Current per power PAD Storage temperature Symbol VDD VI VO IO IPAD Tstg - Conditions
[1]
Value -0.5 to +6.5 -0.5 to VDD+0.5 -0.5 to VDD+0.5 -24 to + 24 -90 to +90 -65 to +150
Unit V V V mA mA C
Tj = 25 C VSS = 0 V
[1] Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the other sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions (VSS = 0 V)
Rated Value Parameter Power supply voltage Symbol VDD Min 2.7 4.5 Operating temperature Input rise/fall time (normal type)[1][2]
[3][4]
Typ 3.3 5.0 +25 2 2 - -
Max 3.6 5.5 +85 500 500 60 200
Unit V V C ns ns s s
Ta trA, tfA trB, tfB
-40 - - - -
Input rise/fall time (Schmitt Trigger type)
trC, tfC trD, tfD
[1] [2] [3] [4]
trA, tfA - TTL interface, normal input buffer. trB, tfB - CMOS interface, normal input buffer. trC, tfC - TTL interface, Schmitt Trigger input buffer. trD, tfD - CMOS interface, Schmitt Trigger input buffer.
Operating Range (VSS = 0 V)
Parameter Supply voltage Ambient temperature Oscillation frequency [1] Symbol VDD Ta fOSC Rated Value 2.7 to 5.5 -40 to +85 30 k to 50 M Unit V C Hz
[1] 50-MHz oscillator frequency for VDD is 4.5 ~ 5.5 V.
OKI SEMICONDUCTOR
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s MSM38S/98S Data Sheet s --------------------------------------------------------------------
DC Characteristics (VDD = 4.5 ~ 5.5 V, VSS = 0 V, Tj = -40 C ~ +85 C)
Rated Value Parameter High-level input voltage Symbol VIH Conditions TTL input CMOS input Low-level input voltage VIL TTL input CMOS input TTL-level Schmitt Trigger input threshold voltage Vt+ VtVT CMOS-level Schmitt Trigger input threshold voltage Vt+ VtVT High-level output voltage Low-level output voltage VOH VOL - - Vt+ - Vt- - Vt+ - VtIOH = 2, 4, 8, 12, 16, 24 mA IOL = 2, 4, 8, 12, 16, 24 mA IOL = 48 mA High-level input current IIH VIH = VDD VIH = VDD(50 k pull down) Low-level input current IIL VIL = VSS VIL = VSS (50 k pull up) VIL = VSS (3 k pull up) 3-state output leakage current IOZH IOZL VOH = VDD VOL = VSS VOL = VSS (50 k pull up) VOL = VSS (3 k pull up) Stand-by current[2] IDDS Output open VIH = VDD, VIL = VSS Min 2.2 0.7xVDD -0.5 -0.5 - 0.8 0.2 - 0.24xVDD 0.6 3.7 - - - 20 -10 -250 -5 - -10 -250 -5 - Typ[1] - - - - 1.7 1.3 0.4 3.1 1.8 1.3 - - - 0.01 100 -0.01 -100 -1.6 0.01 -0.01 -100 -1.6 0.1 Max VDD+0.5 VDD+0.5 0.8 0.3xVDD 2.2 - - 0.76xVDD - - - 0.4 0.5 10 250 - -20 -0.5 10 - -20 -0.5 100 Unit V V V V V V V V V V V V V A A A A mA A A A mA A
[1] Typical condition is VDD = 5.0 V and Tj = 25 C for a typical process. [2] RAM/ROM should be in power-down mode.
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OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
DC Characteristics (VDD = 2.7 ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C)
Rated Value Parameter High-level input voltage Low-level input voltage CMOS-level Schmitt Trigger input threshold voltage Symbol VIH VIL Vt+ VtVT High-level output voltage Low-level output voltage High-level input current VOH VOL IIH Conditions CMOS input CMOS input - - Vt+ - VtIOH = 1, 2, 4, 6, 8, 12 mA IOL = 1, 2, 4, 6, 8, 12, 24 mA VIH = VDD VIH = VDD (100 k pull down) Low-level input current IIL VIL = VSS VIL = VSS (100 k pull up) VIL = VSS (6 k pull up) 3-state output leakage current IOZH IOZL VOH = VDD VOL = VSS VOL = VSS (100 k pull up) VOL = VSS (6 k pull up) Stand-by current[2] IDDS Output open VIH = VDD, VIL = VSS Min 0.7xVDD -0.5 - 0.24xVDD 0.1xVDD 2.2 - - 5 -1 -120 -2 - -1 -120 -2 - Typ[1] - - 2 1 1 - - 0.01 35 -0.01 -35 -.55 0.01 -0.01 -35 -.55 0.1 Max VDD+0.5 0.3xVDD 0.76xVDD - - - 0.4 1 120 - -5 -.120 1 - -5 -.12 10 Unit V V V V V V V A A A A mA A A A mA A
[1] Typical condition is VDD = 3.3 V and Tj = 25 C for a typical process. [2] RAM/ROM should be in power-down mode.
OKI SEMICONDUCTOR
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s MSM38S/98S Data Sheet s --------------------------------------------------------------------
AC Characteristics (Core VDD = 5 V, VSS = 0 V, Tj = 25 C)
Parameter Internal gate delay times Inverter 2-input NAND 2-input NOR Inverter Driving Type 1x 1x 1x 1x 2x 4x 1x 2x 4x 1x 2x 4x CLK to Q D to CLK CLK to D FO = 1, L = 0 mm Input tr/tf = VDD /1.0 ns Output loading: FO = 2, L = 2 mm L = Metal length Conditions Input tr/tf = VDD /1.0 ns Output loading: FO = 1, L = 0 mm Rated Value [1][2] 0.20 0.25 0.28 0.47 0.35 0.22 0.57 0.36 0.25 0.69 0.53 0.51 1.63 1.5 0.1[3] 500 Unit ns
ns
2-input NAND
ns
2-input NOR
ns
Flip-flop (FD1A)
Delay time: Set-up time: Hold time:
ns MHz
Toggle frequency of flip-flop
[1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type. [2] Characteristics are quoted for a typical process. [3] thL (C,D)  0.1 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table.
AC Characteristics (Core VDD = 3.3 V, VSS = 0 V, Tj = 25 C)
Parameter Internal gate delay times Inverter 2-input NAND 2-input NOR Inverter Driving Type 1x 1x 1x 1x 2x 4x 1x 2x 4x 1x 2x 4x CLK to Q D to CLK CLK to D FO = 1, L = 0 mm Input tr/tf = VDD /1.0 ns Output loading: FO = 2, L = 2 mm L = Metal length Conditions Input tr/tf = VDD /1.0 ns Output loading: FO = 1, L = 0 mm Rated Value [1][2] 0.31 0.38 0.43 0.72 0.54 0.34 0.87 0.55 0.38 1.06 0.81 0.78 2.66 2.29 0.15[3] 327 Unit ns
ns
2-input NAND
ns
2-input NOR
ns
Flip-flop (FD1A)
Delay time: Set-up time: Hold time:
ns MHz
Toggle frequency of flip-flop
[1] For the purpose of this table, Rated Value is calculated as an average of the LH and HL delay times of each macro type [2] Characteristics are quoted for a typical process. [3] thL (C,D)  0.15 ns. For I/O information, please refer to the AC Characteristics listed in the I/O table.
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OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
AC Characteristics (I/O VDD = 3.3 V or 5 V, VSS = 0 V, Tj = 25 C)
Rated Values For V LL 3-V Ext 3-V Core HL 3-V Ext [3] 5-V Core
DD Conditon [1][2]
Parameter Input buffer delay times
Type TTL input
Conditions Input tr, tf = 0.2 ns/3.3 V FO = 2, L = 2 mm[4] Input tr, tf = 0.3 ns/5 V (LH, HH) tr, tf = 0.2 ns/3.3 V (LL, HL) FO = 2, L = 2 mm [4] 4 mA 8 mA 16 mA 24 mA 2 mA 4 mA 8 mA 12 mA CL = 20 pF CL = 50 pF CL = 100 pF CL = 150 pF CL = 20 pF CL = 50 pF CL = 100 pF CL = 150 pF CL = 150 pF for 24 mA buffer [5]
LH 5-V Ext [3] 3-V Core
HH 5-V Ext 5-V Core
Unit
-
-
-
0.82
ns
CMOS input
0.95
1.78
0.96
0.71
ns
Output buffer delay times
Push-pull for HH & LH
(tin = 0.3 ns/5 V for LH & HL or tin Push-pull for LL & = 0.2 ns/3.3 V for HL LL & HL)
- - - - 2.30 3.11 3.34 3.76 - - - -
- - - - 1.53 1.99 2.18 2.58 - - - -
2.90 3.86 3.87 3.69 - - - - 3.38 (r) 3.59 (f) 9.20 (r) 7.86 (f)
1.39 1.86 2.03 2.51 - - - - 2.66 (r) 3.04 (f) 3.60 (r) 3.62 (f)
ns
ns
Output buffer transition time (20-80%)
Push-pull Push-pull with slew rate control
ns ns
[1] [2] [3] [4] [5]
Rated values are calculated as an average of the L-H and the H-L delay times for each macro type. Characteristics are quoted for a typical process. Parameters include level shifter cell where appropriate. For L = 2 mm, metal capacitance value of 0.304 pF has been chosen. Output rising and falling times are specified.
OKI SEMICONDUCTOR
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s MSM38S/98S Data Sheet s --------------------------------------------------------------------
MACRO LIBRARY
Examples NANDs NORs EXORs Flip-flops Latches Flip-flops Combinational logic
Basic macrocells
Basic macrocells w/ Scan test
Clock tree driver macrocells Macrocells Output macrocells 3-State outputs Push-pull outputs Open drain outputs Slew rate control outputs PCI Outputs
MSI macrocells
Counters Shift registers
Mega macrocells Macro Library Input macrofunctions
RTC SCSI
UART, 82Cxx PCI, PCMCIA
Inputs Inputs w/pull-ups
Inputs w/pull-downs
Bi-directional macro-functions Macro-functions MSI macrofunctions
I/O I/O w/pull-ups
I/O w/pull-downs PCI I/O
74199 74163
74151
Oscillator macrofunctions
Gated oscillators
Memory macrocells
SOG RAMs (single- and multi-port) SOG ROMs
Optimized diffused RAMs (Single- and multi-port) Optimized diffused ROMs
Figure 4. OKI Macro Library
MACROCELLS FOR DRIVING CLOCK TREES
OKI offers clock-tree drivers that guarantee a skew time of less than 1.0 ns. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include:
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* Clock skew  1.0 ns * Automatic fan-out balancing
OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
The clock-skew management scheme is described in detail in the 0.8m Technology Clock Skew Management Application Note .
Clocked Cell Main Trunk Sub Trunk Branch
* * * * * *
Dynamic sub-trunk allocation Single clock tree driver logic symbol Single-level clock drivers Automatic branch length minimization Dynamic driver placement Up to four clock trunks
Clock Drivers
Pad
Input Buffer
Clock Tree Driver Macrocell
Figure 5. Clock Tree Structure
OUTPUT DRIVER MACROCELLS FOR SLEW RATE CONTROL
The slew-rate-control output driver macrocells reduce both simultaneous-switching noise and outputringing noise. The output transistors are split into two sets; first, one set of output transistors drive the output pads, then, after the output passes the threshold, the second set of output transistors drive the I/O pads. Figure 6below shows output drivers configured for slew-rate control. All outputs with a drive of 8 mA or more are available with slew-rate control.
First Set of Output Transistors From Internal Node Output Pad Switch Second Set of Output Transistors
Figure 6. Slew Rate Control Output Buffer
OKI SEMICONDUCTOR 11
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
AUTOMATIC TEST VECTOR GENERATION
OKI's 0.8m ASIC technologies support Automatic Test Vector Generation (ATVG) using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage  95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction
Scan Data In D C SD SS
Combinational Logic A B FD1AS Q D C SD SS Q Scan Data Out
FD1AS
QN
QN
Scan Select
Figure 7. Full Scan Path Configuration
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------------------------------------------------------------------- s MSM38S/98S Data Sheet s
DESIGN PROCESS
Level 1 [4] Schematics CDC [1] Floorplanning Simulation VHDL/HDL Description Test Vectors CAE Front-End
Level 2 Netlist Conversion (EDIF 200) Scan Insertion (Optional) CDC [1] Floorplanning Pre-Layout Simulation (Cadence Verilog) Test Vector Conversion (OKI TPL [3]) TDC [2]
Level 2.5 [4] Layout (Silvar Lisco Gards) Fault Simulation [5] (Cadence Verifault or IKOS) OKI Interface Automatic Test Vector Generation (Synopsys Test Compiler)
Verification (Cadence DRACULA)
Post-Layout Simulation (Cadence Verilog)
Level 3 [4] Manufacturing Prototype Test Program Conversion
[1] [2] [3] [4] [5]
OKI Circuit Data Check program (CDC) verifies logic design rules OKI Test Data Check program (TDC) verifies test vector rules OKI Test Pattern Language (TPL) Alternate Customer-OKI design interfaces available in addition to standard level 2 Standard design process includes fault simulation
Figure 8. OKI Design Process
OKI SEMICONDUCTOR
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s MSM38S/98S Data Sheet s --------------------------------------------------------------------
OKI ADVANCED DESIGN CENTER CAD TOOLS
* Floorplanning for front-end simulation and back-end layout controls * Clock tree structures improve first-time silicon success by eliminating clock skew problems * Power calculation which predicts circuit power under simulation conditions to accurately model package requirements
Vendor Platform Sun
[2]
Design Kits
Cadence
Operating System SunOS Solaris [3]
[1]
Vendor Software Composer Verilog Veritime Verifault Synergy Concept Leapfrog Composer Verilog Veritime Verifault Synergy Composer Verilog Synergy Alchemy IDEA QuickVHDL QuickSim II QuickPath QuickFault QuickGrade AutoLogic DFT Advisor
[1]
Description
Design capture Simulation Timing analysis Fault grading Design synthesis Design capture VHDL simulation
HP9000, 7xx
HP-UX
Design capture Simulation Timing analysis Fault simulation Design synthesis Design capture Simulation Design synthesis Simulation Fault grading Design capture VHDL simulation Logic simulation Timing analysis Fault grading Fault grading Design synthesis Test synthesis Compilation Design synthesis Test synthesis VHDL simulation Design capture Simulation VHDL simulation Timing analysis Design migration Design synthesis Simulation
IBM RS6000
AIX
IKOS Mentor Graphics
Sun [2]
SunOS Solaris [3] HP-UX SunOS Solaris [3]
HP9000, 7xx Sun [2]
Synopsys
(Interface to Mentor Graphics, VIEWLogic) Sun [2] HP9000, 7xx IBM RS6000 Sun [2] PC
SunOS Solaris [3] HP-UX AIX SunOS Solaris [3] DOS Windows Windows NT[3]
Design Compiler HDL/VHDL Compiler Test Compiler VSS Workview Plus Powerview Vantage Optium ViewTime/Motive [3] ViewRetargeter ViewSynthesis ViewSim with VSO
VIEWLogic
[1] Contact OKI Application Engineering for current software versions. [2] Sun(R) or Sun-compatible. [3] In development.
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OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
PACKAGE OPTIONS
MSM38S0000 42-Alloy QFP Package Menu
Master Slice MSM38S...
QFP (42-Alloy)
I/O Pads[1]
44
q
60
q
80
q
100
q q q
128
136
144
160
0110 0210 0300 0570 0980 1500 2250
100 136 160 216 280 344 420
q q q q
q q q q q q q q q q q q q
Body Size (mm) Lead Pitch (mm)
9.5 x 10.5 0.8
15 x 19 1
14 x 20 0.8
14 x 20 0.65
28 x 28 0.8
28 x 28 0.65
28 x 28 0.65
28 x 28 0.65
[1] I/O pads can be used for input, output, bidirectional, power, or ground signals. q = Available now
MSM38S0000 Cu-Alloy QFP and TQFP Package Menu
Master Slice MSM38S... 0110 0210 0300 0570 0980 1500 2250 QFP (Cu-Alloy) I/O Pads [1] 100 136 160 216 280 344 420
q q q q q q q q q q q q q q q
TQFP 272 304 44[2]
q q
176
208
240
64 [2]
q q q
80 [2]
q q q q
100 [2]
q q q q
144[3]
q q q q q
Body Size (mm) Lead Pitch (mm)
24 x 24 0.5
28 x 28 0.5
32 x 32 0.5
36 x 36 0.5
40 x 40 0.5
10 x 10 0.8
10 x 10 0.5
12 x 12 0.5
14 x 14 0.5
20 x 20 0.5
[1] I/O Pads can be used for input, output, bidirectional, power, or ground signals. [2] 1.0mm thick [3] 1.4mm thick q = Available now
OKI SEMICONDUCTOR
15
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
MSM38S0000 PLCC and CPGA Package Menu
Master Slice MSM38S...
PLCC
I/O Pads[1]
CPGA 84 88
q q q q q q q q q q q q q q q q q q
44
q q q
132
176
208
401
0110 0210 0300 0570 0980 1500 2250
100 136 160 216 280 344 420
Body Size (mm) Lead Pitch (mm)
17x17 1.27
28x28 1.27
33x33 2.54
35x35 2.54
38x38 2.54
44x44 2.54
50x50 1.27
[1] I/O Pads can be used for input, output, bi-directional, power or ground. q = Available now
16
OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
MSM98S000 QFP Package Menu
Master Slice MSM98S... 020x020 023x023 026x026 029x029 032x032 035x035 038x038 041x041 044x044 047x047 050x050 053x053 056x056 059x059 062x062 065x065 068x068 071x071 074x074 077x077 080x080 083x083 086x086 089x089 092x092 095x095 098x098 101x101 104x104 Body Size I/O Pads
[1]
PQFP (42-Alloy) 44
r q q r r r r r r r r r r r r r r
PQFP (Cu-Alloy) 136 144 160 176 208 240 272 304 44
r r
TQFP 64
r r r r r q q
60
r r r r r r r r r r r r r r r r r
80
r r r r r r q q r r r r r r r r r
100
128
80
r q r q r q r q r
100
80 92 104 116 128 140 152 164 176 188 200 212 224 236 248 260 272 284 296 308 320 332 344 356 368 380 392 404 416
r r r r r q r q r r r r q r r q q q q q q r q q q q q r q q q q q r r q q q r r q q q q q q q q r q q q q q q q q r q q r r q q r q q q q q q q q q q q q q q q q r q q q r r r r q q q q q q q q q q q q q r r r q q q q r r r r q r r q r r r r r q q r r r r q r q q r q q r r q q q q q q q r r q r q r r r r r q q q r r r r q r r r r r q q
q q q r
q q q r q r q q r r q q q q r
r
q q q q r r r r
9.5 x 10.5 0.8
15 x 19 1
14 x 20 0.8
14 x 20 0.65
28 x 28 0.8
28 x 28 0.65
28 x 28 0.65
28 x 28 0.65
28 x 28 0.5
24 x 24 0.5
32 x 32 0.5
36 x 36 0.5
40 x 40 0.5
10 x 10 0.8
10 x 10 0.5
12 x 12 0.5
14 x 14 0.5
Lead Pitch (mm)
[1]
I/O pads can be used for input, output, bidirectional, power, or ground connections.
q = Available now r = In development
OKI SEMICONDUCTOR
17
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
MSM98S000 PLCC and CPGA Package Menu
Master Slice MSM98S... 020x020 023x023 026x026 029x029 032x032 035x035 038x038 041x041 044x044 047x047 050x050 053x053 056x056 059x059 062x062 065x065 068x068 071x071 074x074 077x077 080x080 083x083 086x086 089x089 092x092 095x095 098x098 101x101 104x104 Body Size Lead Pitch (mm) PLCC I/O Pads 80 92 104 116 128 140 152 164 176 188 200 212 224 236 248 260 272 284 296 308 320 332 344 356 368 380 392 404 416 17 x 17 1.27 28 x 28 1.27
[1]
CPGA 84 72
r r r q q q q q q q q q q q q q q q r r r r r r r q q q q q q q q q r r r r r r r r r r r r q q q q q q q q q r r r r r r r r r r r r r r r r r r r r r q q q q q q q q q q q q q q q q q q q q q r r r r r r r q q q q q q q q q q r r r r r r r r r r r q q q q q q q q q
44
r r r q q q
88
132
176
208
28 x 28 2.54
33 x 33 2.54
35 x 35 2.54
38 x 38 2.54
44 x 44 2.54
[1] I/O pads can be used for input, output, bidirectional, power, or ground signals. q = Available now r = In development
18
OKI SEMICONDUCTOR
------------------------------------------------------------------- s MSM38S/98S Data Sheet s
OKI SEMICONDUCTOR
19
s MSM38S/98S Data Sheet s --------------------------------------------------------------------
20
OKI SEMICONDUCTOR
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